Month: December 2023

Hardware (FPGA) Assisted Emulation: Part 2

JasonLeave a comment

Our goal for today is to create a simple tile based render engine on the fpga. Lets break down some of the things it will need.

First, what will it do? Lets go simple.

We are going to render to our 240x240 pixel screen (because thats what I have setup today).

I want a single layer of tiles where each tile is 8x8 pixels. Lets make the map big enough to render 256x256 pixels (32x32 tiles). The only fancy feature we will add is the ability to scroll the tile map and control if it wraps around or if it cuts off when you get to the end of it.

Lets do a 256 color palette where each color is a 16bit RGB565 color.

Simple enough...

First, we need some ram:

For the tile map we want a single byte per tile. This byte will simply be an index into tile graphics memory, later on we may add tile flipping or other features to the tile. Since our map is 32x32 tiles we need 1024 bytes to hold the map.

Tile graphics will be represented by 8x8 tiles where each pixel is represented by a single byte which maps to a color in the palette. Since we can only address 256 tiles our tile graphics memory will be 8x8 * 256 = 16KB.

The palette is pretty easy...just 256 16-bit entries for 512 bytes of data.

Finally, We need a single array of ram to hold a rendered line. Lets render in RGB565 format (5 bits red, 6 bits green, 5 bits blue). Lets go ahead and make this line 256 pixesl wide because powers of two make life much easier on fpga. We could have done 240 to save a bit of space. Each pixel is 2 bytes (RGB565) so we need 512 bytes of data for this line.

That should be it for graphics ram.

Next, we will need and SPI implementation. Sure, we could probably just take one off the shelf or from an IP library but I have a little secret...SPI is just a shift register...we got this.

We are also going to want two GPIOs, one to indicate the frame is done (vertical blank interrupt) and one to indicate a line is done (horizontal interrupt). Both of these will be one way from FPGA to MCU. To keep things simple we will ensure we wait long enough each line to ensure the MCU has time to copy it all.

Finally, we just need an x and y counter to loop through all the pixels on the screen...this will address a tile in the tile map, use that to grab the right tile graphics from the tile memory and then use those graphics to find the right color in the pallet and then finally stuff that into the array we made to hold the display line.

We will come back and figure out how to make ti scroll and wrap and all that jaz in a bit.

And that sums up what we are going to be doing. The next part will be setting up the FPGA tools and hooking them up to our retro watch so we can get to developing!

Hardware (FPGA) Assisted Emulation

JasonLeave a comment

I wanted to take some time to talk about one of the really cool features of the Retro Watch: the FPGA and how it works in conjunction with the DA14706 main application processor. What better way to do that than with a demo!

Lets start with a basic system block diagram:

The main application CPU feels like it was created just for the Retro Watch. It has a LOT of ram for an embedded MCU (over 1MB) and that ram is very well partitioned to avoid bus conflicts when doing data moves behing the scenes (very important for rendering graphics without making the rest of the CPU pause).

And it has an absolutely absurd amount of QSPI ports. The first is actually an 8 bit SPI port (though currently we are only using half its potential with a 4 bit spi flash chip). It then has two memory mapped QSPI busses which can directly drive FLASH or PSRAM chips. In our case, an 8MB PSRAM chip provides extra ram for projects that need it; its not very fast ram but it does have a 4KB cache to speed things up a bit. The other QSPI port is connected to the FPGA. This port is both for configuring the FPGA on start up and for communicating with it while running. This gives us a moderately fast memory-mapped interface which is pretty specacular. Notice the PSRAM QSPI bus is also connected to the FPGA. This allows the FPGA to utilize the PSRAM directly, or eaves drop for some hacky memory tricks.

Finally, there is a QSPI specifically for the LCD. While our design actually uses the much faster MCU bus (a parallel 8 bit bus for talking to LCDs) it does give us the flexibilty to support a wider range of LCDs in the future (if we decide the front display should be EINK for instance).

The GPU is pretty basic. It has two hardware layers that can do on the fly color format conversion and color keying. It also has a simple blitting engine which can blit 2D buffers about without loading down the CPU (again, supporting various color format conversions on the fly). The blitting engine does some simple scaling and antialiasing but thats about as exciting as it gets. Even as limited as it seems, this frees up a LOT of resources compared to software rendering and makes our 160Mhz CPU into a pretty narly 2D graphics renderer in its own right.

BUt probably the coolest thing about this GPU (for us) is that you can put the blit textures and the hardware framebuffers anywhere in memory...including the memory-mapped QSPI buses! Why is that cool? I can memory map the FPGA directly into a framebuffer and poof: we have an infintantely configurable, cycle accurate, graphics core we can match up to pretty much any 2D game console that requires almost no interaction from the CPU for the actual rendering (okay, so there are some memory concerns for anything too far past snes era stuff but someone clever might be able to do N64 or PSX).

Not going to lie, I love everything about this project but its the FPGA that really gets me excited to develop on it.

Lets go through a simple example of how we might use the FPGA to render graphics. We are going to take it easy on ourselves and not try to sync up the LCD rendering with FPGA rendering and just make a simple Tile Map renderer that renders one line of pixeles at a time. It will then raise an interrupt to let us know when its done so we can copy it to a fraembuffer, and then moves on to the next line.

Part 2 is comming soon!